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New lead developer for RPCEmu emerges

Published: 1st Dec 2008, 23:06:01 | Permalink | Printable

Dick Tanis steps forward as the new maintainer for the open source RiscPC emulator, together with a couple of coding pals, to continue development of Tom Walker's software. At the moment, the Linux port of RPCEmu remains a priority. Tom stepped down from the project earlier this year.

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This is fantastic news. I use only Linux at home now, so further development on what has been a promising project so far is most welcome if it will enable me to continue to have access to my RISC OS data.

I will try to help by submitting bug reports when time allows, and encourage others to do the same -- even if you're a non-techie type, it's something you can do to help the project along.

 is a RISC OS Usertamias on 2/12/08 11:14AM
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Do I take it that the emulator is a translator from ARM machine code to C? Linux is not cpu specific, after all.

 is a RISC OS UserGavinWraith on 2/12/08 2:07PM
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It has two compile time modes.

Interpreted - ARM to C, which should work on any processor architecture [1]

Dynamic Recompilation - ARM to x86-32 and x86-64 machine code, a more direct mapping for these two architectures, that should offer a speed boost, but only on those specific architectures. In theory further target CPU architectures could be supported.

[1] In reality there are still a couple of endianness issues that need to be resolved for big endian processors such as PPC and Sparc.

 is a RISC OS Userflibble on 2/12/08 2:28PM
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What is the likelihood of improving on native hardware speed using either the Interpreted or Dynamic Compilation modes available under RPCEmu? Is it likely that Iyonix performance will be exceeded using RPCEmu + Linux on a typical x86 dual-core processor rated at 2 or more Ghz: 1) straight away; 2) only after considerable development; 3) never.

 is a RISC OS Userbucksboy on 2/12/08 3:22PM
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There are two types of dynamic recompilation which are commonly used; block and optimised.

The block method involves breaking down each target instruction in to a series of very simple operations and building a buffer of branches to the 'blocks' of native code which implement the operations. Then instead of interpreting the instructions again, the buffer of branches is executed. This can be done either with native instructions or higher level C code on any architecture (with a small drop in performance).

The second method is optimised dynamic compilation, and this involves assembling a buffer of native instructions corresponding to each of the simplified operations the emulated instruction has been broken down in to. Several passes over this buffer are made to remove redundancy such as writing a value to the emulated register bank at the end of one operation and having to read it back again again at the beginning of the next, and only computing the processor flags which will actually be used by later instructions.

Virtual RPC uses the first block method and gives better than StrongARM but less than Iyonix level of instruction emulation performance on contemporary PCs. The second method would make the emulation many times faster than an Iyonix, and if done well close to native x86 performance, but its also a lot more effort.

But for either method taking advantage of x86-64 will give significant advantages, both reducing register scarcity and allowing the entire ARM physical address space to be mmap'd, reducing complexity.

 is a RISC OS Userdruck on 3/12/08 2:18PM
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druck: Indeed. If you're really careful, you can represent all the important ARM registers in AMD64 registers. And using mmap() carefully gives you swap for free. (ie, just emulate a machine with 2GB of RAM, regardless of how much RAM the host machine has.)

 is a RISC OS Userrjek on 3/12/08 7:51PM
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