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XScale Clarification

By Peter Naulls. Published: 18th Apr 2003, 10:48:00 | Permalink | Printable

RiscStation Spin Doctor busy again

There seems to still be a fair amount of confusion about XScale processors. This is reasonable enough, it's still a relatively new thing. However, this has been recently compounded by confusing statements made by RiscStation's spokesperson. We'd like to take this opportunity to clarify some points, in our usual, lucid no-nonsense style.

Thanks to David Ruck and Hedley Simons for clarifying and checking some points.

If you've got any further questions, drop us a line, and we'll see what we can do about answering them.

Disclaimer: I am not a hardware engineer.


"XScale is a machine on a chip like the 7500FE"

Doubly incorrect. Firstly, the term "XScale" in general terms refers to Intel's range of processors which supersede the StrongARM. This family contains quite a number of members. In technical terms, "XScale" refers to the processor core, or the bit that actually handles the ARM instructions.

The 7500FE by contrast, is a specific chip (although it does have several versions), which is found in several RISC OS machines including the A7000 and RiscStation machines.

The specific XScale used in Castle's Iyonix machine is the Intel 80321 I/O Processor, also referred to as the 80321 or IOP321. This chip contains a great deal of functionality which makes it a good choice for a desktop RISC OS machine, including a PCI controller and I2C bus.

The IOP321 doesn't have a video or audio controller, nor any functionality to talk directly to the outside world. In the Iyonix, video and sound are provided by PCI cards, and a separate Southbridge chip contains functionality for IDE, serial, USB and power management. The Iyonix also contains some other logic to help simulate parts of the RiscPC hardware. This is some way from a machine on a chip solution.

By contrast, the 7500FE does contain most of the functionality around which you could build a computer, including video, audio, serial ports (but no PCI). This has made it a popular choice for RISC OS machines in the past.


"A machine with seperate chips will run faster than an integrated one like the IOP321"

This is a red herring. The machine's maximum speed is governed by one thing - its processor speed. Access to other devices depends upon how things are put together, and the existence of any bottlenecks (such as the infamous slow RiscPC bus). In fact, a machine with an integrated chipset will tend to run faster due to less latency between devices. Finally, the overall speed of the machine is governed by the speeds and architecture of specific devices (whether integrated or not).

(I have intentionally not mentioned DMA here for simplicity)


"The XScale doesn't give clock for clock performance compared to the StrongARM"

Careful. It's true that the XScale processors clocked at 400Mhz in some early iPAQs didn't perform any better than comparable StrongARM devices. In searching for the answer, people suggested that the issue was the compiler not optimising for XScale. It's also true that you can get some improvement by optimising correctly, but most of the reason came down to architectural issues.

By contrast, the 600Mhz IOP321 in the Iyonix has no such issues, as quickly becomes evident if you use a machine for a short while. Benchmarks show the relative performance to be within a few percent.


"Why didn't Castle choose the faster 733Mhz XScale?"

Although 733Mhz IOP200 is clocked ~20% faster, it only has a 100Mhz bus compared to the 200Mhz one found in the IOP321, and doesn't contain as much functionality suitable for a desktop machine.


"What about the 1Ghz ARMs?"

It's not clear when these might be available. It's also been claimed that the 733Mhz IOP200 could be overclocked to 1Ghz, but I can't confirm the veracity of this.


"Will the Iyonix processor be upgradeable?"

Only if Intel produce a pin-compatible IOP321 processor. Even then, it will be a specialist job. Anything else will require a new motherboard, which may be desireable anyway, if Castle make improvements in other areas.


"Any futher questions?"

Contact me at peter@chocky.org.


Links


ARM 7500FE Data Sheet (PDF)
XScale Product Brief (PDF)
Intel IOP321 I/O Processor

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Discussion

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Excellent article. Hopefully this will stop people being confused by people who don't know what they're talking about

 is a RISC OS Usertakkaria on 18/4/03 11:07AM
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I agree, more articles like this please. Sets the record straight, particularly on the separate chips issue. How much to put on a single chip is largely down to economics, your yeild from a wafer goes down considerably as die size is scaled up. On chip buses are of course faster and more power efficient.

 is a RISC OS Userrob on 18/4/03 11:20AM
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I am happy to accept requests for article on specific topics, but of course make no promises. I can also accept stuff that you've written (even if it's just notes), but not in a publishable state, that I can tart up.

-- Peter, drobe.co.uk

 is a RISC OS Usermrchocky on 18/4/03 11:24AM
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Excellent article. Please note 3 small criticisms. 1) 'veracity' contains an 'a', 2) 'separate' contains 2 'a's, 3) 'supersede' does not contain a 'c'.

 is a RISC OS UserGavinWraith on 18/4/03 11:51AM
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I think this really cleas up the current issues. I even undestood it! (I'm 14) What impressed me was an advert I saw for the new XScale intergrated chip (the type where everything is on the chip) next to an NEC phone that could use it. It is TINY and supports everything from USB to GSM, GPRS , audio, video. Imagine if this were in you're Iyonix, you wouldn't be able to find it and internet connection is instant! (Look Mum! No wires!) ----------- Smiler - :D Alex Melhuish

 is a RISC OS UserSmiler on 18/4/03 12:10PM
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Well done mr. Naulls.

This way other 12 year olds finally know the inner issues of RISC OS machines. And it might prevent other bullshit from appearing.

Keep up the good work.

 is a RISC OS UserEPDM on 19/4/03 9:44AM
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Well laid out and lucid article Peter (take a bow).

If *anyone* (and I am not mentioning *anyone* by name in this) ignores this and persists in insisting that the IOP321 (ala Iyonix) is like a 7500FE it will be plainly obvious that such an individual is being willfully dishonest.

I'd also add the point that AMD's Opteron (aka Claw/Sledgehammer) has the memory controller integrated on the same chip as the CPU precisely for to maximise performance and minimise bottlenecks (so one could more liken the IOP321 to a state of the art 64bit processor than the venerable old 7500FE).

Again nice article Chocky......

-- Annraoi McShane,

 is a RISC OS UserAMS on 19/4/03 5:24PM
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There's also the IBM Power 4 with two CPU's, three cache controllers and 1.5Mb of cache on a single die... that's not like a 7500FE! -- Rob

 is a RISC OS Userrob on 19/4/03 10:39PM
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Thanks Peter. It is nice to see a well written article stating the facts clearly. -- Cheers Steve

 is a RISC OS Userknutson on 19/4/03 11:25PM
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rob: I'm sure HP have been doing that with HP-PA for ages. (More than one CPU core on a single dye)

 is a RISC OS Usernunfetishist on 20/4/03 10:54AM
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Didn't realise that... but Power 4 has a lot more than 2 CPU's, there's the above mentioned plus directory for a L3 cache and very elaborate cache coherancy hardware for building huge shared memory multiprocessors. Anyway... we both agree on the point that in the supercomputer/workstation class it becomes economic to put a hell of a lot onto a chip. With an Xscale it's also economic because the CPU core is tiny, relative to something like a Pentium.

 is a RISC OS Userrob on 20/4/03 12:41PM
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Not only there is the economic aspect of integrating more than one functionality block on one chip die, but such a design also allows to go for much less power consumption. The more external chip pins a chip needs to drive, the more power is consumed. A second aspect is that it also allows you to go for higher bus speeds (at expense of power).

 is a RISC OS Userjoty on 20/4/03 1:36PM
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Absolutely... shorter wires -> less capacitance -> less power to drive.

 is a RISC OS Userrob on 20/4/03 7:23PM
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