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ARM two Thumbs up

By Chris Williams. Published: 17th Jun 2003, 12:29:43 | Permalink | Printable


ARM yesterday wheeled out details of their new Thumb-2 instruction set at the Embedded Processor Forum, California. The Thumb-2 instruction set, "builds upon the existing ARM instruction set architecture", according to ARM.

ARM's Thumb architecture squashes their 32 bit instruction set (the fundamental program code that the microprocessor can execute) into 16 bit form to increase efficiency and performance, which is surprisingly useful in the embedded arena. The Thumb-2 architecture blends the 16 bit set with the 32 bit set.

"Thumb-2 core technology uses 26 percent less memory than pure 32-bit code", said ARM's Embedded CPU manager, Richard Phelan.

ARM, originally spun off from Acorn in the early days, are the designers behind the RISC processors present in all RISC OS computers. Nowadays, ARM is best known as a leading provider of embedded processors for devices from PDAs to mobile phones to STBs. Also, ARM designs chips and licenses the blueprints of which to other manufacturers (like Intel), who then make the actual devices.

Despite the ability to mix 16 bit and 32 bit instructions, we'll have to see if Thumb-2 has any effect whatsoever on future RISC OS software and operating systems, however we imagine ARM Linux will be most likely affected as it follows ARM into PDAs and other embedded platforms. CNET isn't expecting Thumb-2 chips for another two years.

Alex Waugh, who first emailed us about the ARM news as a nudge in the direction of where our processor architecture is heading, commented to us, "While [the Thumb-2 news] doesn't give much detail, and isn't directly RISC OS related it is nevertheless a significant development of the ARM architecture."

Incidentally, the ARM website frontpage reads, "Chances are that you have just used an ARM Powered product within the last hour, minute or second". Which is delightfully true given the ARM610 powered mobile and StrongARM RiscPC on this desk.



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It's a shame that Thumb's such an ugly revolting fudge. It doesn't really provide any more code density, or power efficency. In quite a lot of cases, it provides completely the opposite. I suppose we can all blame Nokia for it, anyway.

 is a RISC OS Usernunfetishist on 17/6/03 2:23PM
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God knows what compiler you've been using then, Bob. For things I've seen Thumb used for, it's certainly been worthwhile.

 is a RISC OS Userimj on 17/6/03 2:28PM
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You're on google news sci/tech page: [link]

 is a RISC OS Usermavhc on 17/6/03 4:46PM
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Although not stated outright, there is an implication that Intel just license a design from ARM and build it on silicon. This is certainly not true of the XScale.

What ARM have done for the StrongARM and XScale is license the Instruction Set Architecture (ISA), which Digital (for the StrongARM) and Intel (for the XScale) designed (with input from ARM). Both of these designs are (as far as I'm aware) owned by Intel, but they need a license from ARM to be able to produce them, as ARM owns patents on the way the ISA works.

-- Dougal

 is a RISC OS UserDougal on 17/6/03 7:27PM
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i like a nice bit of cod with my chips

 is a RISC OS Usernex on 18/6/03 6:30AM
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imj: ARM's.

 is a RISC OS Usernunfetishist on 18/6/03 1:50PM
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Dougal: IIRC, the ARM instruction set has no patents on it (Acorn published it into the public domain well before ARM Ltd. even existed). What *does* have patents all over it is Thumb, however. And you wouldn't want to use that anyway. :)

Does XScale do Thumb? I don't recall.

 is a RISC OS Usernunfetishist on 19/6/03 10:37AM
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nunfetishist: I'm fairly sure that ARM have patents on the basic 32 bit ISA. I've read stuff being parented about the way the registers are swapped as you change mode, etc. And I'm sure that's just one of many. There was a discussion about this last month on comp.arch if anyone is really interested.

In addition the StrongARM does not do Thumb code, and yet Digital and Intel had to get licenses to use it.

-- Dougal

 is a RISC OS UserDougal on 19/6/03 12:11PM
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I've just been told by an ex-ARM employee, than anything in ARM3 has no patents on it, as a rule of thumb, so to speak.

 is a RISC OS Usernunfetishist on 19/6/03 2:36PM
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Correction, just to be sure: Nothing in the ARM3 *instruction set* has any patents on it.

 is a RISC OS Usernunfetishist on 19/6/03 2:41PM
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I think the interesting stuff in comp.arch is in this thread:

[ [link] (groups.google.com) - Ed]

Sorry for the long URL

-- Dougal

 is a RISC OS UserDougal on 19/6/03 2:45PM
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I think g0tai needs to fix that - it's made the article 3 pages wide in Oregano :-)

-- Peter, drobe.co.uk

 is a RISC OS Usermrchocky on 19/6/03 2:49PM
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Oops. That broke it :)

-- Dougal

 is a RISC OS UserDougal on 19/6/03 2:49PM
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Note that someone may have already mentioned this on the newsgroups - I haven't scanned all of them so far.

If the patent's only to do with partially banked registers, then it'll be possible to make a 26-bit ARM processor which doesn't do this, but when you enter an interrupt, you copy the unbanked registers from the user mode to the interrupt mode, thus emulating banking in software without actually using partial banks. This veneer would consume a small amount of CPU, but it does mean that we can keep our 26-bit stuff safe, and future proof.

That's if people still want 26-bit mode to be in existance. I personally don't mind if we move over to 32-bit (but I wouldn't want only one machine manufacturer to support it).

 is a RISC OS Usertribbles2 on 19/6/03 3:57PM
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