Signal Description
2.0 Signal Description
	Name		Pin		Type	.
						. . Description
	BOUT	35	OA	Blue Analog Output. The video signal analog outputs are designed to drive
		.	doubly-terminated 75S1 Iines directly into, CRT.
	BUSCLK	109	I	Memory Bus Clock. When configured for a synchronous has interface, this
			dock drive, both VIDC20 and the memorv svstem. It is used to latch data
			during sound and video DMA,. BUSCLK must be tied low in async mode.
	DIN[63:0]	108-89,	I	Data Bus ln. All data to the chip is supplied on this bus. Data for register
	86-71,		programming is always supplied on the lower half of the bus. When in async
,	6841		32 bit mode, a8 data is supplied on the lower half of the bus, and the upper 32
			bits should be had low. When using VRP.M, video data only is supplied on the
			upper half of the bus, and all other data on the lower half. When in split bank
			mode, interleaved DRAM provides 64 bit data du=g DMA,. See Chapter 3.0
			System Configurations for details on architectures.
	ECLK	20	Olfi	Extemal Clock. When enabled, this clock validates the data on ED[7:01. In
			normal video mode, it runs at the pixel rate, but when LCD data is being pm
			duced, it runs at a quarter of the pixel rate.
	ED[7:0]	11-18	OS	Extemal Data. Thesis the digital output port of the chip. From this, the digital
			equivalent of the analog output may be produced in any colour, or data from
			the extemal palette may be produced. This may be used for a variety of
			purposes such as fading, supremacy, or serialisation for driving high
			resolution monitors. Also, data for driving LCD panels is output from this
			port. Data produced is validated by ECLK.
	EREGII:O)	5,6	058	Extemal Register Data. The data from these pins is bits 1 and 0 of the extemal
			register. They may be used to control external devices.
	ESEL11:01	7-8	I	Extemal Data Select These two bits determine the external port output. This
			may be either digital red, green or blue data, extemal data, or LCD data.
	FLYBK	1	058	Fly Back. This gives irSOrmation about the vertical display. It gces high at the
			start of the first raster not in display, and goes low again on the first raster in
	.		the acflve display. Frame buffer updates should be made during the fly back
			period for a flicker free display. .
	GOUT	36	OA	Green Analog Output. The video signal analog outputs are designed to drive
			doubly-terrzilnated 750 lines directly into a CRT.
	HCLK	111	I	High speed CI«k.See Chapter 5.0 Pixel Clock for details of the d«ks.
	HSYNC	27	O$	Horizontal Synchronisafion. There are two synchronisation outputs on
			VIDC20, HSYNC and VSYNC. Dependent on the state of bits 17 and 16 in the
			external register, either horizontal or a composite (NOR) sync may be output
			on this pin, in either polarity. The width of the HSYNC pulse is definable in
			units of 2 puels.
I LSI	24	OA I	Left Analog Sound. Analog left hand stereo channel sound output.
Table 1: Signal Description