System Configurations
3.0 System Configurations
VIDC20 has a 64 bit data bus and there are four basic modes of bus operation.These are described below, with ARM memory controller examples. VIDC20 can be used with any memory controller which supports quad-word DMA-e.g. ARM's MEMC10.
3.1 Asynchronous 32 bit mode.
This is the simplest mode, and in this configuration VIDC20 behaves almost exactly like VIDC10. Only the lower 32 bits of the data bus are used, and the upper 32 bits, though ignored, must be tied low.
VIDC20 makes requests for data to MEMC10 via the nVIDRQ line, and MEMC10 supplies the address to the single bank of DRAM of the next four words to be used. The four words of data come from the DRAM into the lower 32 data bits of VIDC20 and from there directly into the video FIFO within VIDC20.
Similarly, VIDC20 requests data for the hardware cursor sprite when it is required (during the horizontal sync time), and this is supplied as four words out of a different area of the DRAM. This data passes into the same lower 32 data bits of VIDC20 and from there into the cursor FIFO within VIDC20. Finally, the registers within VIDC20 must be programmed. This is achieved by a processor write of the data into VIDC20 register addresses. Again the data is passed to VIDC20 on the lower 32 data bits. MEMC10 has an asynchronous DMA interface (i.e. the synchronisation is carried out within MEMC10). To configure VIDC20 for this mode, the BUSCLK input must be tied permanently LOW, the SM bit in the Data Control Register set LOW, and BUS[1:0] in the Data Control Register programmed to value Ol.
The frame buffer consists of a linear image in the DRAM. The start and end addresses of the buffer are programmable in MEMC10. The cursor buffer also consists of a (much smaller) linear image in the DRAM. The start address of this buffer is also programmable in MEMC10.
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System Data Bus
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VIDC20
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Memory Controller
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Figure 3: ViDC20 connected in Asynchronous 32 bit mode