VIDC20 Data Sheet
3.2 Synchronous 32 bit mode
This mode can be identical to the above mode, with the memory controller and VIDC20 both programmed to have an asynchronous interface like MEMC10 (BRA = 0), or the memory controller and VIDC20 can be configured to have a synchronous interface (SnA =1). The latter is recommended, as it is more efficient and permits interlace to function correctly. Except for programming of the SM bit, this mode is identical to the MEMC10 mode described above and so BUS[I:0] is programmed to value Ol again. This mode must be configured if dual-panel LCDs are to be used.
3.3 64 bit mode
This is the standard configuration, and is an extension of the above mode. Again VIDC20 makes requests for data to the memory controller via the nVIDRQ line, but now the memory controller supplies the address to two banks of DRAM of the next eight words to be used. The four double-words of data come from both DRAM banks into the 64 data bits of VIDC20 and from there into the video FIFO within VIDC20 as 8 words. The two banks of DRAM we separated by a set of biditectional buffers, and a simple PAL is required to control the DRAM enable lines and the buffets.
In this mode both the memory controller and VIDC20 must be programmed to have a synchronous interface (SnA = 1). VIDC20 is configured by setting BUS[1:0] to value 11 in the Data Control Register.
qsrol
System Data Bus
Dlw.azl
DRAM Bank 0
I [- j L R,10, nRAS Memory	noeo Controller
RA(J EO
nOE, ,WE
nVIDFK Controller
VIDC20
D
Figure 4: VIDC20 connected in 64 bit mode