System Configurations
3.4 Split Bank mode
This configuration, is similar to the above, except that in this mode VIDC20 always receives video data on the upper 32 data bits only, and it receives cursor and programming data on the lower 32 bits only. Hence in this configuration the cursor and programming data come from one bank of DRAM, and the video data comes from a separate bank of RAM, which may be DRAM or VRAM. This mode is primarily intended for use with VRAM, and more details are given in the nest section. If DRAM is used, then a buffer would be needed to separate the buses, and a simple PAL to control them. For split bankmode, VIDC20 is configured by setting BUS[1:0] to value 10, and SM= 1.
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System Data Bus
VIDC20
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Memory Controller
Figure 5: VIDC20 connected in Split Bank mode
3.5 Using VRAM with VIDC20
Where very high bandwidth displays are required, VIDC20 should be programmed into split bank mode, and split serial port VRAM used for the frame store. The advantage of this configuration is that although there is a very high transfer rate from memory to VIDC20, the system bus is not used. Split serial port VRAM must be used to ensure that video data transfers are not interrupted whilst transfer cycles take place.