VIDC20 Data Sheet
0131:01
System Data Bus
VIDC20
~ r----I~ DSF
~-l	Ir V	I/	I	I	r--I Do Iw:3z1
Memory Controller
RAp,nRRS,nCRS wioao, nsrvoao,
Figure 6: Using VRAM with VIDC20
A brief description of the interface is given here. For more details, please refer to Applications Note A075 "VIDC20 VRAM Interface", available from Advanced RLSC Machines.
The video data transfer works as follows. When the video FIFO within VIDC20 is ready to accept more data, the nQCLK output is enabled, and this docks the VRAM SAM register four times. The resulting four words of data are then read into the video FIFO. When all of one half of the SAM register has been read, the VRAM's QSF output changes state. This edge is used by VIDC20 to generate nVIDRQ. This goes straight to the memory controller as normal, but generates a VRAM transfer cycle.
VIDC20's nQCLK output is derived from the pixel clock Bits (7:0] of the Control Register are used to select the pixel clock frequency, and bits [17:16] of the Data Control Register select what division of this frequency is output as nQCLK. The frequency of nQCLK should be chosen such that the data rate into the video FIFO is greater than or equal to the data rate out of the FIFO.
For example, a system running with a pixel rate of 80MHz at 8 bits per pixel (bps) consumes data at a rate of SOMByte/s. Therefore, the minimum frequency that the SAM register should be clocked at is 20MHz, (Data Control Register [17:16] = 11). Under these conditions, there would be a continuous transfer of data from VRAM to ViDC20. If a higher nQCLK frequency were chosen, then the transfer would become more
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