System Configurations
'bursty', like a normal DMA. It is important to note here that when video DMfts are happening continuously, sound DMP.s and programming can still occur. This is because activity on the upper and lower buses is totally independent.
In general, the algorithm for the minimum nQCLK frequency is; nQCLK=Pixel-frequency z bpp / 32
and the data control register is then programmed accordingly.
Due to the high load on nQCLK, it must be externally buffered and inverted before driving the VRAMs. The output from the buffer must be fed back into VIDC20 on the QCLK input. This ensures that, at the high frequencies involved, dock skew does not effect the validity of data sampled by the chip.
3.5.1 Dual Banks of VRAM
This is an extension of the above mode, where two interleaved banks of VRAM are used. This allows even higher bandwidth displays (e.g. SOMHz pixel rate at 16bps) to be used. The nQCLK output from VIDC20 should then go to an extemal divide-by-two circuit. The resulting positive and negative dock signals are then used to dock the SAM registers of the two banks of VRAM. For example, a system with a pixel rate of SOMHz and lbbps requires data at 160MBy[e/s. Therefore, if nQCLK is programmed to half the pixel rate, 40MI-Iz, and externally this is halved to produce positive and negative docks, then each bank of VRAM produces data at 20MWord/s, or SOMByte/s, giving the required total of 160MByte/s.
3.6 Display Options
Irrespective of the above configuration used, VIDC20 is capable of many different display formats. In addition to the normal linear CRT display, VIDC20 can generate a true interlaced display, or can generate a display suitable for either single or dual-panel LCDs.
3.6.1 Interlaced Display
When the memory controller is used, interlaced displays may be generated where the image created in the video buffer is the same irrespective of whether interlace is turned on or not. When interlace is turned on, the address generator displays every other raster in the video memory in each field. Two fields make up a complete frame.
3.6.2 LCDs
This is described in more detail later, but the dual-panel LCD option allows VIDC20 to output 2 data streams simultaneously, with one stream for each panel of a dual-panel LCD. The image created in the video buffer is the same irrespective of whether this mode is selected or not. This mode can be programmed to generate 1,2, or 4 bits/pixel grey-level displays. The memory controller is required, and the 32 bit data bus mode must be selected when using the dual-panel (duplex) mode. This restriction is imposed by the memory controller.