Programming Model
4.1.1 Video Palette: Address OH
All entries of the video palette are written at address 0. In order to write any or all of the palette locations, the address pointer must first be written, as described below. The palette is programmed with a 28 bit word representing the physical data field.
31 30 29 26 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 7 6 5 4 3 2 1 0
0 0 0 0 E E E E19 B B B B B B 8 G G G G G G G G R R R R R R R R
Ext	Blua	Green	Red
Physical Calour	Physical Colour	Physical Colour	Physical Colour
4.1.2 Video Palette Address Pointer. Address 1H
The address pointer is programmed at address 1, and it may be programmed to any value from 0 to 255. The first write to the palette will then occur at this location, and the address pointer will post-increment so that the next palette write will occur to the following location. The counter will wrap around from 255 to 0. Once the address pointer has been written, any number of palette locations can be programmed, and the pointer can be reprogrammed at any time if only part of the whole palette is to be updated.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 7 6 5 4 3 2 7 0
lo 0 0 1	x x x x x x x x
Palette Location
4.1.3 LCD Offset Registers: Addresses 30H and 31H
These two, eight bit registers define the offsets required for driving a dual panel LCD screen. Register 0 defines the offsets for the five and two frame duty cycle grey scales, as well as reset and test mode bits. Register 1 defines the offsets for the nine and fifteen frame duty cycle grey scales.
31 30 29 20 T7 26 25 24 23 22 21 21 19 10 17 16 15 11 13 12 11 10 9 0 7 6 6 6 3 2 1 0
10 0 1 11 00 001	x % x x x x x x
`011_2
~ OM _6 ~ mse4201 Im
31 30 29 26 27 26 25 24 23 22 21 20 19 10 17 16 15 14 13 12 11 10 9 0 7 6 5 4 3 2 1 0 I 0 0 1 11 0 0 0 0	X X % % % % X % Y ~ 011_9 11-011_15
17