Programming Model
4.1.25 Frequency Synthesizer Register (fsynreg): Address DH
VIDC20 is able to drive a VCO to provide a suitable input frequency for the pixel clock derived from a reference dock. This is achieved by dividing the reference dock by modulus t, and the VCO dock by modulus v, and comparing the resulting-frequencies. Refer to Chapter 5.0 Pixel Clock for a more detailed explanation. The two moduli, r and v are each 6 bit values, and are programmed in this register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 8 5 4 3 2 1 0
1 -1-17 1	x x x x x x x x x x x x x x x x
modulus r (ref clock)
r test bit,
modulus v (VCO dock)
v test bits
Associated with each counter are 2 test bits which should normally be programmed to 0.
Setting bit[6] forces the phase comparator HIGH, which drives PCOMP HIGH. Setting bit[7] dears the r-modulus counter.
Setting bit[14] forces the phase <ompamtor LOW, which drives PCOMP LOW. Setting bit[15] dears the v-modulus counter.
To reduce power consumption, this register should be programmed with large values when the frequency synthesiser is not in use. In particular, bits [6] and [14] should not be set at the same time.
To get a modulus of r, then value (t-1) should be programmed into the fsynreg. Likewise for the v-modulus.
4.1.26 Control Register (conreg): Address EH
The main control register determines the basic operation of the chip. In particular the pixel dock source, the pixel rate, the number of bits/pixel, the control of the video FIFO, and the data format are programmed. In addition there is a 4 bit test register which must be programmed to zero for normal operation.
31 30 29 28 27 26 25 24 23 22 21 20 1 1 1 01
19 16 17 16 15 14 13 12 71	10 9 8	7 6 5	6 3 2	7 0
X X X X	X	X X		X X X	X X X	X X X	X X
	I I	u	u	u	u
TEST Pew" INT	FIFO Lead	BITSNixel	Pixel Rate	Pixel SOUrca
DOW Normal Dewc	News	000 7	NO CK	IN VCLK
0001 Test CLK pUP	001 4	001 2	001 CIV2	Ot HCLK
cold Test HiIM	6108	0104	010 CK/3	10RCLK
0311 Teat VTIM	011 12	011 B	071 Cq4	
0100Test HDW	10016	100 16	IN CW5	
0101 Test DPATH	10120	101 N/5	101 MB	
0110TesIVDAC	11024	11032	770CK/7	
1000Test SDAC	11126	ill VS	ill cm	
10(i LCD				
1110T851PCOMP