VIDC20 Data Sheet
The pixel dock (pixclk) is selected from one of 3 sources, corresponding to the respective input pins, and the selected clock is then fed through a prescaler as defined by the 3 bits conreg[4:2]. The output of this prescaler is the actual pixel dock. See Chapter 5.0 Pixel Clock for more detail.
The Video FIFO can be programmed to have any number of quad words loaded into it at the start of display. The value chosen should take into account the bandwidth of the display as well as the latency of the DMA subsystem. Refer to Chapter 3.0 System Configurations before programming these values.
If int is set, then VIDC20 will generate a display with interlace syncs. Otherwise, non-interlace syncs will be generated. If a true interlace display is required, then the memory connoller must also be set up to generate an interlace display, as defined in the memory controller datasheet, and the HDW register in VIDC20 set up accordingly.
Setting the dup bit configures the display for dual-panel LCDs. This is described further inChnpter 10.0 Liquid Crystal Displays, but note that the memory controller must also be configured for this type of display.
Note that after a reset the Control Register should be the first register programuted. The Power Down bit (14) must immediately be programmed LOW. The test registers bits (16 to 19) also should be programmed LOW, as any other setting will inhibit normal operation.
4.1.27 Data Control Register (DCTL): Address FH
This register controls the way in which the external 64 bit bus is controlled. The control bit SnA defines the type of bus transfer to be expected for the DMAs. Generally, if MEMC10 is driving VIDC20, then SnA should be programmed LOW, and the BUSCLK input tied low. If the memory controller is fitted, SnA should be programmed HIGH, and BUSCLK should be connected to the DRAM memory dock.
VIDC20 can work in several different bus configurations, as described in Chapter 3.0 System Configurations. Data for programming the device, and data for the cursor and sound FIFOs is always presented on the lower 32 data bits (D[31:0]). Data for the video FIFO can be presented on the lower 32 bits only or the upper 32 bits only, or as 64 bits at a time. These modes are defined by the programming of BUS[1:0]. Note that if SnA is programmed to be 0, then BUS[1:0] must be programmed to be Ol.
31 30 29 26 27 26 25 24 23 22 21 20 19 18 17 16 75 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1	IX X X X	X %	IX X X % % % % X X XI
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When using VIDC20 with VRAM, bits [19:18] must be programmed. These define the division of the pixel dock that is used to dock the VRAM (refer to Chapter 3.0 System Configurations for details). When the system memory does not contain Video RAM, these bits must be programmed to zero to save on power.
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