Programming Model
The horizontal display width is also defined in this register, and should be programmed to be the number of words of data in a displayed raster. It must be programmed in most configurations of the device, as it inhibits a DMA request near the end of a raster, when there are enough words in the video FIFO for that raster. The request is uninhibited after the HSYNC at the start of the next raster. When driving a dual panel LCD screen, this register must be programmed with twice the number of words in a displayed raster. This is a new feature to VIDC20, arid for full compatibility with VIDCIO, it may be disabled. This is achieved by programming bit 13 high.
Programming the horizontal display width has two functions: in normal mode, VIDC20 may be programmed so that the number of bits in a raster is a multiple of 32 (not 128 as is the case with VIDC10); in interlace mode the memory controller can safely update the video pointer during H3YNC time. In interlace mode, the number of bits in a raster must be a multiple of the number of words first loaded into the FIFO at the start of display. Note that if SnA is programmed to be 0, then the HDINR value is ignored (program bit 13 to 1), and the request is not inhibited near the end of the raster.
4.1.28 Stereo Image Register 0-7: Addresses AOH-A7H
These are 8, 3 bit registers which define the stereo position for the eight possible channels, as defined in Chapter 13.0 Sound.
31 30 29 26 27 28 25 24 23 22 21 20 19 16 17 16 15 14 13 12 71 70 9 6 7 6 5 4 3 2 1 0 0	1	0 I0	%	X xl~ ~ ~	I%	X	X
SIR address	SIR value
4.1.29 Sound Frequency Register. Address BOH
This 8 bit register specifies the byte sample rate of the sound data. It is defined in units of lus. See Chapter 13.0 Sound for more detail.
31 30 29 26 27 26 23 24 23 22 21 20 19 16 77 16 15 14 13 12 11 10 9 6 7 6 5 4 3 2 1 0 I1 0 1 1 10 0 0 0'	x x x x x x x x
RFR value
If a sample rate of N ILS is required, then N-2 should be programmed into the SIR N may take any value between 3 and 256.