Pixel Clock
5.0 Pixel Clock
VIDC20 is capable of generating a display at any pixel rate up to 100MHz. The pixel clock may be selected from one of 3 sources, and then the frequency of this clock may be further divided down by a factor of between 1 and 8. These attributes are programmed by the lower 5 bits of the control register.
If a maximum of 3 master frequencies are sufficient, then the clock inputs can be used directly. However, it is often a requirement to have many different master clock frequencies. In order to obviate the need for many crystals on the PCS, VIDC20 is designed to drive a Voltage Controlled Oscillator (VCO to provide the master frequency. The VCO and filter are external to VIDC20, but everything else is built into the chip. Operation is as follows.
A reference frequency is supplied on the pin RCLK. This reference signal will come from a crystal oscillator external to VIDC20, and it is recommended that the frequency, F,,f+, is 24MHz. The signal from the VCO is input into ViDC20 on the pin VCLKIN. VCLKOUT is simply the inverse of VCLKIN, and this may be used to bias the input signal about the threshold if the VCO output is not a full amplitude signal. The VCO output should be reasonably square if operation at 100MHz is to be achieved.
The reference clock is divided by a programmable number set by the r-modulus in the fsynreg. The VCO clock is divided by a programmable number set by the v-modulus in the fsynreg. Each of the moduli may be a b bit number. The output of each of these dividers is fed into a phase comparator, and the result is output from VIDC20 as PCOMP. This pin should then be filtered and used to control the VCO output frequency. In this way, the VCO can be set to have a frequency of v/r' Fin.
The phase comparator is of the phase-frequency type. The output PCOMP is normally iristate, but when the VCO frequency needs to be decreased the output is LOW, and when the VCO frequency needs to be increased the output is HIGH. Whim the 2 frequencies are in lock, PCOMP will normally be tristate, but will be driven to the mid point for a very short time (a few ns) every r/F,ef* period. The output impedance of this pin when it is driven is about 5052.
The choice of filter and VCO is left to the user. It is important to avoid any low-frequency modulation of the VCO frequency. It has been found that a suitable VCO is a 74AC04 inverter element with feedback, with the supply voltage controlled by the PCOMP output. See Application Note 77: "VIDC20 Clock Sources".
With this approach, an enormous number of frequencies are possible. The recommended F,ef of 24MHz can be used to yield the following common VCO frequencies. For some frequencies, there are many possible values of r and v. In this case it is sensible to choose a set of values which favours the filter response. (Remember large moduli yield a lower comparison frequency).
It may be best to limit the VCO range, and use the prescaler within VIDC20 to get a lower pixel rate than the VCO frequency. It is expected that the VCO range may have to be constrained so that it cannot provide the highest frequencies at which VIDC20 can operate. In this case, a single high-frequency dock can be fed into VIDC20 on the HCLK pin, and this can be selected for the pixel clock.