Setting the FIFO preload value
6.0 Setting the FIFO preload value
The Video FIFO is a 32 entry, 32 bit wide FIFO. Words of video data we clocked into the top of the FIFO under control of BUSCLK and nVIDAK. In 64 bit mode, two words are loaded into the FIFO on each clock cycle. Words are clocked out of the bottom of the FIFO as the video system displays the data, which is controlled by the pixel clock.
The FIFO is flushed during vertical flyback time, so before the start of the frame the FIFO is empty. At the start of the frame a video request is made to the memory system by asserting nVIDRQ. When a predetermined number oŁ words have been loaded into the FIFO the request is removed. As the data in the FIFO is displayed, further video requests are made to refill the FIFO to the desired level.
The Control Register includes a 3 bit field (bits 10:8) to set the preload value of the Video FIFO. In this way the FIFO can be programmed to load 4,8,12,16,20,24 or 28 words of data into the FIFO at the start of frame. Note that in 64 bit bus mode, the memory system will deliver data in blocks of 8 words, so programming the preload value to be an odd number will result in the FIFO filling to the next even value. After the start of frame, the FIFO will request more data when the number of words in it falls below the preloaded value.
The point at which the FIFO should request more data to be loaded is dependent upon system considerations: if the FIFO is reloaded too late, there is a danger that it will run out of data (underflow); if it is reloaded too early, then there is a danger that the data will not fit into the FIFO (overflow). In general, the higher the bandwidth of the screen, then the more words need [o be preloaded into the FIFO. In a low bandwidth screen mode, it is not always desirable to have a large preload value, as the bus traffic will have long bursts of data transfer at the start of the frame.
The optimum value to be preloaded depends upon the screen mode in use (ie the rate at which data is read from the FIFO), and both the latency of the memory controller and the rate at which data is provided to VIDC20. It is generally prudent to program the minimum value possible to keep the bus traffic even.
Let:
n	be the value programmed into the control register.
v	(words/ps) be the rate at which video data is displayed
lmax	(lts) be the maximum latency in the memory system. (This is the maximum time between VIDC20 requesting more video data and the memory system delivering the first word of that data).
Imin	(ys) be the minimum latency in the memory system.
Pb	(lts) be the period of BUSCLK
If the FIFO is almost empty then it takes O.OSus for a word of data to reach the bottom of the FIFO before it can be used.
The minimum value for n is deduced from the following condition to avoid the FIFO undexflowing:
There are 4n words in the FIFO when the FIFO requests more data, and if not refilled, then the FIFO would be empty in 4n/v us. The request from the FIFO is synchronised to BUSCLK before rtVIDRQ is asserted to the memorv controller. This takes a maximum of 2P6.
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