VIDC20 Data Sheet
11.3 Vertical and Horizontal Synchronisation
Software control over the polarities of the synchronisation pulses is provided. Two types of Composite Sync may be output, each of either polarity. The logical OR of Hsyn< an Vsync may be output on the Horizontal Sync (HSYNC) pin, and the XOR of Hsync and Vsync may be output on the Vertical Sync (VSYNC) pin. Equalisation pukes in the composite synchronisation signal are supported for interlace mode. When LCD mode has been selected, the extemal HSYNC and VSYNC pulses are modified in accordance to the requirements of an LCD screen.	.
The HSYNC and VSYNC pins are programmed with the Ext Register, ereg(19:16].
In addition to the above, VIDC20 outputs another signal named VnC, (Video /not Cursor) for memory controllers to use to discriminate between video and cursor requests. VnC is unaffected by the configuration of the HSYNC and VSYNC pins.
11.4 Genlocking
Genlo<king support identical to that on VIDC10 is provided: a pin is provided to reset the vertical counter to the first raster (SINK), and the horizontal locking is achieved by comparing the phase of the HSYNC pulses and phase-locking the input clock. In addition, the chip outputs FLYBK.
FLYBK goes HIGH at the start of the first raster which is not active display (but may be in the border), and goes LOW at the start of the first raster which is active display. FLYBK thus gives information about the vertical timing.