In reply to Simler:
The RISC verses CISC debated ended long ago, as no CISC processor has run the x86 ISA since the 486. All chips since then have a RISC core that operates on microinstructions that bear absolutely no relation to the x86 instructions. The nasty nasty x86 opcodes are translated by the first few stages of the pipeline, and where as this was a significant overhead on the first pentiums, the vast transistor buget of todays processors makes the decoding insignificant in terms of resources. Thats no to say a well designed RISC instruction set (register rich, three operand) such as POWER can't thrash the x86, in terms of instruction density, instructions per clock and efficent utilisation of chip resources.