If the IOP342 contains all the peripheral features of the current chip, which it seems to, then only there would only need to be a redisgn for the differing package layout, plus of course any other changes such as an updated southbridge which would be needed. The seperate flash to hold the ROM could be deleted as it has 32MB on board.
The 1.2GHz clock speed increment combined with the Level 2 (undoubtedly only 512K) would give a substantial speed boost over the IOP321. The 1MB of internal memory could be used to hold critical parts of the OS for further performance gains. This just may hit the 3x tipping point for Castle to consider an Iyonix Mk2.
Thats only considering single core perforamance of course, as currently RISC OS has no facilities to make use of multiple processors. How to utilise the 2nd core would be the big question, symetric multi-processing is obviously not feasible with a CMT OS model, but farming out certain operations which could run in parallel such as I/O handling, graphics rendering and sound synthesis would be possible.
It unlikely Castle would have the resouces to serious tack this, so it would be the ideal case for open sourcing some/all of the OS, as it would allow developers to tack managable chunks of work. As long as the OS establishes a frame work for mutlicore use, operations could be migrated over from the primary processor in a piecemeal fashion.