All DDR is SDRAM, and although usually in DIMM packages, SO-DIMM packaging is available. (I do not mean that DDR is
the same as SRAM, of course.)
I agree with you that 66MHz/64b is the native maximum;
I am saying this is equivalent to 133MHz/32b. This means the
logic to convert between 64b and 32b is inside the ARM already.
I don't see how reducing memory latency below processor latency
would help: The memory would be faster than the processor,
and therefore only called at the maximum speed of the processor, ie wasted. With sufficient cache, a main store speed
half that of the processor (if "single data rate" used) should be good enough, that is, increasing the speed of the memory to
that of the processor would not double the overall system speed.
Nonetheless, I may have confused references to the
Iyonix's use of DDR with the Kinetic somewhere along the line.
I don't see why the Kinetic can't use DDR, the question is
if CTL intended it to be used.
(And the answer to the question why didn't CTL run the memory
at 133MHz instead of 66MHz, is that it was (if DDR used) already being accessed at that rate, clock speed regardless.)