First of all, why am I not surprised that half the comments here are negative even though what was demoed at the Wakefield Show was undeniably a positive step for RISC OS?
Next, we've done quite a few RISC OS ports in the past and to say that this is just a small step and all the hard work is yet to come is just plain wrong.
Getting _anything_ happening it the hardest part, especially if you don't have access to JTAG, MultiICE, etc. Then, you can get bits of the HAL working and maybe bits of the kernel. After that, you bung some more modules in and look for problems.
You might need to do a lot or a little work to get some peripherals working (e.g. USB).
Then, you bung the rest in and fix a few remaining issues. For the most part, that bit doesn't take much time or effort - it's very much an exponential graph of progress.
For someone who is new to the RISC OS sources and who has never done a RISC OS port before to have got things this far is both a great reflection of their skills and of the design of the HAL.
In the particular case of the Beagle port, I expect the most trouble from now on will come from strange effects of the subtle changes to the ARM instruction set in the V7 architecture.