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Ah, I see your point now. Yes, CSD (and other) consistency is an issue if the OS expects to be able to interrupt a program preemptively. If you're still running CMT but on two cores, applications still don't get interrupted like that, but you do have two applications running at once. I guess you'd need two copies of the CSD, the sprite context, and, er, interesting things like the system volume.

Regarding filecore, asynch apis would let well written applications poll while waiting for I/O. Sure, it'd be a beast to write for, but then writing for CMT has always been fundamentally harder than writing for a PMT system (assuming an underlying os that has per-process state).

Lets face it, RISC OS that supported pre-process state, PMT and SMT wouldn't really be RISC OS any more. I'm just thankful (with my RISC OS hat on) that they're still making ARM cores with outrageous clock speeds, and that the promise of multicore chips with lower clock speeds hasn't yet come to pass.

 is a RISC OS Userninja on 22/5/09 2:02PM
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