No, really; instruction timings, memory access speeds, contents of system control co-processor registers, core features, etc, all differ wildly. Sheeva's a marketing term, and their efforts to merge the multiple different core designs (such as XScale and Ferocean) under one roof.
Now it couldn't be simpler to send us your news We've added a form to the front page so you can quickly and easily submit your news, links, tip-offs or anything else RISC OS-related that you think other Drobe readers will be tickled by. Submitting news helps us keep the Drobe front page regularly updated and if your news is posted, we'll give you a byline so you can let everyone know you're doing your bit for Drobe, the RISC OS platform's top source for news, views and information. Discuss this. Published: 23 Feb 2009