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It will be fully backwards compatible with instruction set that we are using on current systems from an application developers point of view, some of the X-Scale only instructions wont be supported, but there is very little non hardware specific code using those. There would need to be a few changes to operating systems for initialising the new level2 cache control mechanism, but the largest change will be due to the differing subsystems of which ever SOC (System On Chip) is chosen, which all new machines use rather than the old fashioned discrete processor and seperate I/O chipset.

 is a RISC OS Userdruck on 6/10/05 10:41AM
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