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jess: A marginal, but possibly noticable one, yes - half-word (16 bit) loads and stores from memory are frequently of use in things like image decoders and such, and these are the instructions that do not work on RiscPC-class machines. (Less to do with the CPU, and more to do with the IOMD chipset on the motherboard.) StrongARMs can do them if the data is already in the cache, and Kinetics can do them if the data's on the on-board fast RAM.

In any case, Peter's refusal to say why he had decided to make it Iyonix-only in the first instance, when there is demonstratably no technical reason is the own-goal - and the nominations and the vast majority of the voting occured before he did release an A9 Home version. And we don't yet know if the only reason he made his second reason A9 Home-friendly is because we'd got his old one working anyway. He's been completely silent on the matter.

 is a RISC OS Userrjek on 1/1/07 3:49PM
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