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FIQ handlers would indeed be a problem if the vectors were moved to &FFFF0000. I wouldn't exactly describe them as a legacy feature; the Iyonix still supports podule FIQs, and certain ARM-based SoC's have some of their peripherals hard-wired as FIQs. Of course, the RISC OS API could easily be extended to allow the correct address for installation of a FIQ handler to be determined.

Actually, one of the reasons why page 0 has remained unprotected in privileged modes is that it is home to the IRQ semaphore. It's undesirable to require the page tables to be updated (and back again) around every IRQ, and the address is so low in memory that we can't even use the extra-small 1K pages available in modern MMUs to control it independently of the processor vectors and FIQ handler. Ideally, the IRQ semaphore would be moved out of the way, but unfortunately it's one of those magic addresses which some modules "know" about and use directly.

RISC OS 5 added an OS_ReadSysInfo 6 reason code to read the address of the IRQ semaphore, but it probably won't get heavy use until the IRQ semaphore is moved and people find their modules breaking.

 is a RISC OS Userbavison on 25/4/07 10:44PM
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