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> StrongARM binaries will be faster on an XScale than ARM6 ones If that means that the compiler knows about load-use delays and tries to schedule instructions between an LDR Rd,[] and any use of Rd then yes. IIRC unexecuted LDM/STMs are also cost more than 1 cycle on SA so knowing that can also improve performance on the XScale.

Of course, that's knowledge of the SA/XScale's performance characteristics rather than usage of new instructions, but I think that's by far the greatest benefit to be had. Some small improvement may also be gained be use of halfword loads/stores which are new to post-ARM6 CPUs but most of the other new instructions are not really useful to a compiler.

 is a RISC OS Useradrianl on 23/3/04 1:54AM
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