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RISC OS features in plain english By Chris Williams. Published: 14th Jan 2006, 07:08:47 | Permalink | PrintableA brave stab at bringing all the feature lists together into one easy to understand summary
Select 4
The details of what is likely to be in Select 4 was published in October by RISC OS Ltd. It involves the 32bit kernel and operating system produced for the Samsung ARM9 powered AdvantageSix A9 range. Select 4 is hoped to be ready in time for Q2 2006, two years after the release of Select 3.
The features list was mostly lifed from the programmers' logs and is therefore rather on the technical side. Below is an attempt at explaining what the more interesting features mean with a summary in plain english at the end of each section. The text in quotes is from the leaflet handed out by ROL at the 2005 South East Show.
Kernel and other low level work
"All the source is now updated to be 32bit safe. Support for 32bit only processor modes is included. Assembler based components are now built using ObjAsm and a modern makefile."
The kernel is at the heart of the operating system and its job is to act as an intermediary between the application software and drivers that talk to the computer hardware. Whenever a serious error occurs or a device needs controlling, it's typically the kernel that takes over and delegates the task of handling the issue. It has been made compatible with modern 32bit ARM processor cores, opening up the opportunity for it to run, for example, on ARM9 and XScale platforms. The new makefile is part of RISCOS Ltd.'s move towards making their operating system less of a headache to update and improve.
"Kernel has lots of abstraction of its graphics API. It now has no pointer support, abstracted to OSPointer module. Video hardware is now driven by an external module. The only significant change that has yet to be completed is the banking of screen modes. Video hardware abstraction now provided to remove dependency on VIDC and IOMD architectures. VideoHWVIDC provides the entire hardware driver for video. VideoSW provides the software implementation for certain graphical operations."
Previously, the kernel has been tied to the Acorn-era chipset. Now this dependency has been gradually removed, leaving a kernel that can be more easily ported to other ARM based platforms. This includes the graphics hardware driver and mouse pointer support, both of which are in separate modules that can be replaced as desired depending on the requirements of the underlying hardware. As an example, RiscPC class computers will be running the VideoHWVIDC module, whereas A9home users will be using VideoHWSMI - same kernel, different driver modules. A separate module can be provided to implement operations in software that cannot be performed in hardware. For example, the A9home's Silicon Motion SM501 video chipset can accelerate in hardware the copying of rectangular blocks of the screen, whereas the Acorn VIDC in the RiscPC cannot. A separate module could perform this operation in software for VIDC users.
The overall result is that RISC OS becomes even more modular and producing ports for other platforms becomes easier. Replacing and improving individual components and functionality also becomes easier.
According to those close to its development, this is also one of the reasons why 32bit RISC OS 4 cannot use the Castle RISC OS 5 kernel: the way in which the new 32bit kernel and the individual component modules that used to be in the RISC OS 4 kernel communicate won't work with the RISC OS 5 kernel, it's claimed.
"It also now correctly supports LD/ST 'T' and SWP in abort trap mode."
RISC OS provides a degree of memory protection so that if a typical application tries to access a protected or invalid area of memory, it is stopped by what is known as an abort - reported, for instance, to the user as the familiar 'Abort on data transfer' message. Sometimes the operating system may want to be notified when a program accesses a particular area of memory. To do this, the OS marks the area of memory as being out of bounds and waits for the program to use it. When the application does so, the processor will detect the operation, pause the running program and inform the kernel via an abort. In this case, the kernel passes control to a special handler that will silence the abort so that no error message is generated, perform some background task related to the watched area of memory, execute the program's instruction that triggered the abort and then return seamlessly to the application, allowing it to continue as normal. This is used with lazy task switching and accesses to special cached screen areas, where the operating system must intervene if a program attempts to access particular areas of memory.
A similar system exists called Abort Trapping, which works in exactly the same way except it emulates the trigger instruction rather than executing it directly, and device driver developers can use this feature to their advantage: a piece of hardware can be 'mapped' into memory, which means it can be treated as an area of memory where settings can be stored, status information retrieved and commands to be performed written to. Instead of plugging in hardware and mapping it in, during development the device driver programmer can instead opt to just mark the are
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