RISC OS 5 HAL reaches 26 bit usersBy Chris Williams. Published: 24th Mar 2003, 20:48:58 | Permalink | Printable
Theo brings the OS 5 Hardware Abstraction Layer spec to RISC OS 3 and 4Theo Markettos has announced today the release of his HAL26 software, which provides the RISC OS 5 Hardware Abstraction Layer specification to RISC OS 3 and RISC OS 4 - the 26 bit OS variants. A Hardware Abstraction Layer is designed to provide a generic interface to a computer's hardware so that software and the operating system kernel doesn't have to concern itself with device specific details. For example, if a programmer wishes to set a hardware timer countdown, she calls
HAL_TimerSetPeriod - the programmer doesn't care how the computer hardware goes about setting the timer or indeed what specific chip is providing the timer function. It's all about providing a generic interface.
As Theo states in his announcement, his HAL26 module "allows the programmer easy access to interrupt control, timers and counters in a machine-independent manner." The source code to HAL26 is also provided (distributed under the Artistic licence) and is for 26 bit OSes only.
Theo's module essentially provides the
OS_Hardware SWI as defined in Castle Technology's Iyonix HAL documentation and a few
Podule_ SWIs for pre-RISC OS 3.5 machines. The goal is to allow podule drivers and other hardware related code to be written so that they work across the entire RISC OS hardware range, from the A310 to the Iyonix.
HAL26 version 0.04
RISC OS 5 HAL open sourced
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